This invention relates to a semiconductor memory device, in particular, to a semiconductor memory device providing a repair circuit for repairing a defective cell.
In a semiconductor device such as a DRAM or SRAM, all memory cells corresponding to addresses must operate correctly. This means that two hundred and sixty million memory cells must operate correctly in a case of a semiconductor device having a capacity of 256 M bits, for example. Practically, it is impossible to manufacture such a semiconductor memory device including a large number of memory cells so that all of the memory cells may operate correctly.
Therefore, in a related semiconductor memory device, spare selection lines and spare memory cells are previously provided to give redundancy. When there is a defective memory cell, it is replaced by a spare redundant memory cell. That is, in the related semiconductor memory device, normal memory cell and defective memory cell are distinguished by a wafer test and the defective memory cell is replaced by a redundant memory cell as shown in FIG. 1.
Here, it is known that defects of the memory cell include a case where the memory cell is physically broken and a case of so called an operational margin defect which occurs only on specific operating condition. The physical defect is caused by various factors, such as a defect of a reticle, a foreign body introduced into a wafer during impurity diffusion, lack of process margin and so on. There is no way to repair the defective memory cell caused by the physical factor except for replacing by the redundant memory cell as mentioned above.
On the other hand, regarding the operational margin defect, there is a case where it is repaired by timing adjustment of some signal. Therefore, in another related semiconductor memory device, a signal timing adjustment is applied to a memory cell judged defective at a wafer test as illustrated in FIG. 2. When the memory cell applied with the signal timing adjustment operates correctly in an additional wafer test, it is not replaced by a redundant memory cell but repaired by signal timing adjustment. When the memory cell applied with the signal timing adjustment is judged defective in the additional wafer test, it is repaired by replacing by the redundant memory cell. Such a semiconductor memory device is disclosed in Japanese Unexamined Patent Application Publication No. 2004-164737 or No. 2002-74961.